1. Technical Field
The present disclosure relates to the field of high-speed downlink packet access, and more particularly to increasing the throughput of a memory in a turbo decoder at a receiving device.
2. Related Art
Turbo coding is a high-performance coding scheme. Each data bit to be communicated (“subject data bit”) is represented by a group of control bits, such as error correction bits. The group of control bits are determined using a recursive systematic convolutional code applied to the subject data bit and a predetermined number of adjacent data bits. An interleaver interleaves two or more groups of control bits into a data block prior to transmission so that if an error burst occurs (an error burst is a contiguous sequence of errors that are not correctable by most lower-performance coding (data recovery) schemes), it will be scattered among the several groups of control bits. At the receiving device, a turbo decoder recovers the correct data by iteratively de-interleaving and decoding the data block.
High-speed downlink packet access (HSDPA) is one communications protocol that allows networks to have higher data transfer speeds and capacity and may implement turbo coding to maximize information transfer in the presence of data-corrupting noise that may cause an error burst. Turbo coding may also be implemented in other high performance communication protocols, such as Orthogonal Frequency Division Multiple Access (OFDMA), Long Term Evolution (LTE), Enhanced Data rates for GSM Evolution (EDGE), Enhanced GPRS (EGPRS), and the like.
A turbo decoder includes a memory (random access memory) in communication with a decoding processor and an interleaver. Processed data blocks are temporarily stored in the memory after each iteration. The data blocks are iteratively processed through the processor, the interleaver, and the memory until a parameter referred to as the logarithm of likelihood ratio (LLR) indicates a high-probability that the subject data bit is either a “0” or “1”. Each iteration through the turbo decoder includes two sub-iterations. The first sub-iteration is referred to as the systematic iteration, where the processor processes the data block, and the second sub-iteration is referred to as the interleaved iteration, where the interleaver assigns a respective memory address to each data block so that data can be read linearly from the memory for the subsequent systematic iteration.
Conventionally, the processing speed of the memory must be sufficiently faster than that of the decoding processor. For example, if a turbo decoder includes two decoding processors operating in parallel, and each processor processes at X MHz, the memory must process at least at 2X MHz so that the processed data blocks can be written to and read out of the memory fast enough to support the parallel processing demand. The performance of a turbo decoder may not be increased simply by increasing the processing speed of the processors.